1. Field of the Invention
The present invention relates to a flash memory array and a method for fabricating the same, and more particularly to a three-dimensional (3D) stacked array having cut-off gate line which enables to operate two memory cells by each word line, to produce a high integrity without limit by vertical stacks of word lines, to increase operating speed and uniformity of electrical property between cells by using a single crystal substrate as a channel region, and to reduce a fabricating cost to a great amount by forming a plurality of trenches in a semiconductor substrate and stacking repeatedly conductive materials interlaid with an insulating layer to have a cut-off gate line and a plurality of word lines from bottom of each trench.
2. Description of the Related Art
These days, flash memories have been becoming popular as non-volatile memories with possibilities of a low power operation and a high integrity. Because main subject leading semiconductor industry shifts personal computers to mobile electric instruments, importance and demand of flash memories have been more increasing.
A conventional flash memory is classified as code flash memory and data flash memory according to its application. The code flash memory uses a NOR type structure flash memory having a short random access time, and the data flash memory uses a NAND type structure flash memory having a short writing time and a high integrity.
Particularly, NAND type flash memories, which have a high integrity because it is unnecessary to form contacts of source and drain on each memory cell, have been used mainly as large capacity storages in portable disks, digital cameras, video recorders, audio recorders and so on.
To meet the above-mentioned demands, flash memory technologies for a high integrity, a low power and a high speed operation are developed continuously.
Recently, because of some limitations in improving integrity degree by cell size reduction based on planar structure, memory arrays having three-dimensional structures have been developing.
The representative prior arts having the three-dimensional structures were described in U.S. Pat. No. 6,878,991 B1 and Korean patent number 777016 of the same inventors of the present invention.
In the prior arts, both embody word lines on each side wall to reduce required areas of total array to a great amount and to produce high integrity. However, the former invention is difficult to make practical use by some problems in fabricating process. Although the latter had an advantage of putting the former to practical use, it has limitation in improving integrity degree due to the formation of a control gate (i.e., word line) per memory cell and the requirement of interval for separating the control gates.
In order to solve the problems in the Korean patent number 777016, Korean patent application number 10-2008-0014125 was filed by the same inventors of the present invention and it was published as Korean publication number 10-2009-0088693.
According to the Korean patent application number 10-2008-0014125, the areas of the interval for separating control gates were reduced by forming one control gate (word line) between two memory cells having a vertical channel and one cut-off gate line under the one control gate in a folded 3D pillar structure. However, it has also limitation in improving integrity degree due to the formation of one control gate (word line) per trench.